module top_clock(Alarm,Hour,Minute,Second,CP,nCR,EN,Adj_Min,Adj_Hour,Alarm_EN,Alarm_Hour,Alarm_Min); input [7:0] Alarm_Hour,Alarm_Min; input CP,nCR,EN,Adj_Min,Adj_Hour,Alarm_EN; output [7:0] Hour,Minute,Second; output Alarm; //定义输入输出端口 wire [7:0]Hour,Minute,Second; wire Alarm; //定义变量数据类型 supply1 Vdd; wire MinL_EN,MinH_EN,Hour_EN; counter10 U1(Second[3:0],nCR,EN,CP); //秒计数器个位 counter6 U2(Second[7:4],nCR,(Second[3:0]==4'h9),CP); //秒计数器十位 assign MinL_EN=Adj_Min? Vdd:(Second==8'h59); //产生分钟计数器使能端信号，Adj_Min=0正常计时，1校正分钟 assign MinH_EN=(Adj_Min && (Minute[3:0]==4'h9))||(Minute[3:0]==4'h9)&&(Second==8'h59); counter10 U3(Minute[3:0],nCR,MinL_EN,CP); //分计数器个位 counter6 U4(Minute[7:4],nCR,MinH_EN,CP); //分计数器十位 assign Hour_EN=Adj_Hour? Vdd:((Minute==8'h59)&&(Second==8'h59)); //产生小时计数器使能端信号 counter24 U5(Hour[7:4],Hour[3:0],nCR,Hour_EN,CP); //小时计数器计时 alarm_clock U6(Alarm,Alarm_Hour,Alarm_Min,Hour,Minute,Second,Alarm_EN,CP); //闹钟功能调用 endmodule module counter6(Q,nCR,EN,CP); //六进制计数器 input CP,nCR,EN; output [3:0] Q; reg [3:0] Q; //定义输入输出端口 always @(posedge CP or negedge nCR) begin if(~nCR) Q<=4'b0000; //清零 else if(~EN) Q<=Q; //暂停，低电平有效 else if(Q==4'b0101) Q<=4'b0000; //满值，返零 else Q<=Q+1'b1; //正常计数 end endmodule module counter10(Q,nCR,EN,CP); //十进制计数器 input CP,nCR,EN; output [3:0] Q; reg [3:0] Q; always @(posedge CP or negedge nCR) begin if(~nCR) Q<=4'b0000; else if(~EN) Q<=Q; else if(Q==4'b1001) Q<=4'b0000; else Q<=Q+1'b1; end endmodule module counter24(CntH,CntL,nCR,EN,CP); //二十四进制计数器 input CP,nCR,EN; output[3:0] CntH,CntL; reg [3:0] CntH,CntL; reg CO; always @ (posedge CP or negedge nCR) begin if(~nCR) {CntH,CntL}<=8'h00; else if(~EN) {CntH,CntL}<={CntH,CntL}; //清零和暂停 else if((CntH>2)||(CntL>9)||((CntH==2)&&(CntL>=3))) {CntH,CntL}<=8'h00; //满值清零 else if((CntH==2)&&(CntL<3)) //小时数小于23 begin CntH<=CntH;CntL<=CntL+1'b1;end //小时数介于20~23，高位不变低位加一 else if(CntL==9) begin CntH<=CntH+1'b1;CntL<=4'b0000;end //低位等于9，低位返零高位加一 else begin CntH<=CntH;CntL<=CntL+1'b1;end //其它情况，高位不变低位加一 end endmodule module alarm_clock(Alarm,Alarm_Hour,Alarm_Min,Hour,Minute,Second,Alarm_EN,CP); //闹钟功能实现模块 input CP,Alarm_EN; input [7:0] Alarm_Hour,Alarm_Min,Hour,Minute,Second; output Alarm; reg Alarm; //定义输入输出端口 always @( posedge CP or negedge Alarm_EN) begin if(~Alarm_EN) Alarm<=1'b0; //检测是否开启闹钟功能 else if((Alarm_Hour==Hour)&&(Alarm_Min==Minute)&&(Second==8'h00)) Alarm<=1'b1; //闹钟时间到，高电平 else Alarm<=1'b0; end endmodule 本文来源：https://www.wddqw.com/doc/aa8e1196dd88d0d233d46a62.html