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Integrated Circuit Design CAD Tool Information This page contains common CAD tool information used for the courses EE E4321 (VLSI Circuits) and EE E6321 (Advanced Digital Integrated Circuit Design). CAD Tool and Technology Information General information Getting started with Cadence 2.6.1 On-line CAD tutorial on Schematic Editor On-line CAD tutorial on Spectre simulation through the Analog Design Environment (ADE) On-line CAD tutorial on Layout On-line CAD tutorial on DRC/LVS with Calibre On-line CAD tutorial on Extraction On-line CAD tutorial on Ultrasim Questions or comments for improvement of this page to shepard@ee.columbia.edu Last Updated : 11/03/2011 EE E4321 - VLSI CIRCUITS Textbook information These books are all on reserve in the Columbia Engineering Library. Required text: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison-Wesley, 2010. Fourth Edition! Other useful books: Rabaey, Chandrakasan, and Nikolic, Digital integrated circuits: a design perspective, Prentice-Hall, 2003. (Please note that this is the Second Edition of the original Rabaey text. Prof. Rabaey's book has become the "industry standard" textbook for introductory VLSI design courses.) Glasser and Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley. (This is an excellent circuits book, although it has unfortunately become a little dated.) Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press. (This is a really excellent device physics book, probably the best one available today.) Uyemura, Circuit Design for CMOS VLSI, Kluwer. Bernstein, Carrig, Durham, Hogenmiller, Nowak, and Rohrer, High Speed CMOS Design Styles, Kluwer. (An excellent "encyclopedia" of practical digital circuits.) Sutherland, Sproull, and Harris, Logical effort: design fast CMOS circuits, Morgan Kaufmann. (Very readable text on gain-based tuning of digital circuits.) D. Harris, Skew-tolerant circuit design, Morgan Kaufmann. (An excellent book for understanding timing issues in digital integrated circuits; a great reference for the lectures on latches and clocking.) [EE4321 HOME] Teaching Lab CAD Tools Information Modern industrial integrated-circuit-design CAD tools will be an integral part of this course. All students must have access to the CAD tool setup at Columbia. This page contains relevant administrative information for all you need to do to get started with these tools. Read the following : You will use the Linux workstations in the VLSI CAD Lab (1218 Mudd) or in the Embedded Systems Lab (1235 Mudd) You need o Swipe/badge access to the lab o An active login ID At the first class, I will collect login information and arrange for badge access and computer accounts. After the first week of class, any problems with badge access should be addressed to John Kazana, the EE department lab manager. Problems with login access to the machines should be addressed to Bill McCabe, the EE department systems administrator. Guidelines for working in the VLSI CAD Lab or Embedded Systems Lab: Both computer labs are managed by EE Department and they have some general guidelines which are to be followed strictly. Failure to comply by these rules generally results in permanent deletion of the account without much discussion. In all cases, it will be extremely difficult for the instructor or TA to restore the account. Do NOT bring any friends/visitors in the lab and let them use the machines on your account. These are not "public" machines, like the CUIT machines. Food and drinks are allowed, BUT you must be VERY careful and clean up after yourself. If you make a mess or damage equipment, we will suspend this privilege and you will be responsible for any damage that you cause. We are very serious about this! The quota for each student is 80 MB. Therefore, it is important that you keep only relevant files in your home. In case, you genuinely need more space, consult the TA. Do NOT fire huge printing jobs at the lab printer. Printers are for your convenience and printing anything other than HW or project files is NOT permitted. We have limited quota on the paper and we have to work within those limits. Also DO NOT try to print tool documentation. Such files are hundreds of pages. Issues regarding printer supplies should be addressed to John Kazana. Do NOT reboot the machines. Several other people might have important jobs running on the same machine. Contact system administrators in case it hangs or freezes. System Administrator : o Bill McCabe [trouble@ee.columbia.edu] Some Facts You need to know.... Default printers should be set correctly for all the machines. When you print from the machines in Mudd 1218, the print-outs will appear on the printer in Mudd 1218. When you print from the machines in Mudd 1235, the print-outs will appear on the printer in Mudd 1235. We encourage doing your homework and projects in the Mudd 1218 and Mudd 1235 labs. This allows the professor and TA to do walk-through and help you. It also allows you to help each other. However, you may log on remotely. Instructions for doing this can be found here. All paths for CAD tools should be automatically set. [EE4321 HOME] Getting Started with Cadence 2.6 This page will help you set up your Cadence environment. In your Linux desktop, you will see a folder named "____'s Home". Inside it make a new folder (directory) named Cadence. This is where you will be running cadence. Open this folder, and right-click your mouse to open a terminal that will look like this: The title of the window contains information about your login and current directory. In the image above, the login ID is 'jaebin', the name of the machine is 'linux8', and the current directory is ' ~/Cadence '. Your home directory is symbolized by the '~' sign, and the ' /Cadence ' part shows that I am in the directory called Cadence. You can do almost anything on this terminal screen, from navigating to other directories (folders) to running software like Cadence. You will need to get used to this screen. Here are a few useful terminal commands that will help you in the future: go up one directory change directory copy all files from directory A to B view current directory view list of files in current directory open pdf make folder at current directory initiate Cadence cd .. cd destinationDirectory cp directoryA/* directoryB pwd ls acroread pdfname.pdf mkdir newname virtuoso & The following four files are needed to set up your Cadence environment: 1) .cdsinit 2) .cdsenv 3) cds.lib 4) display.drf You can copy these from the directory /usr/tools/cds/setup to your Cadence directory (~/Cadence) by typing the following line in the terminal: cp /usr/tools/cds/setup/* ~/Cadence The spaces between commands are exaggerated above, but one space is sufficient in the actual command line. Type "ls" in your terminal to check that all four files have been successfully copied. Now go to your Cadence folder, not your terminal, and change the 'cdsinit' and 'cdsenv' file names to have dots in front of them: '.cdsinit' and '.cdsenv' (IMPORTANT!!). These are files that define your Cadence environment when you initiate the program. Also copy a comptut.pdf by typing cp /usr/tools/cds/doc/* ~/Cadence You will now see that a comptut.pdf has been copied. This is a tutorial for the previous version of Cadence (2.5). A few of the option names and GUI will be different from what you will be using, but it will serve as good reference when you are facing problems with the user interface (shortcut keys, mouse controls, etc). Now we are ready to draw a schematic! Cadence Schematic Editor Information If you haven't read the General information page or the Getting started... page, READ THOSE FIRST. In this handout, we are going to learn how to draw schematics in Cadence Schematic Editor. We will draw a simple inverter in Composer and then do a transient simulation using the Analog Design Environment. Follow the steps : Step1 :Invoke cadence by typing virtuoso & from your ~/Cadence directory. Step2 :Click on Tools--->Library Manager....The library manager window should pop up soon. Step3 :Click on File ---> New ---> Library . Step4 :On the "New Library" window, name your library "yourUNI". Step5 :A "technology file for new Library" window pops up. Click on attach to an existing technology library and click cms9flp . Step 6:Your library should now be listed in the library manager's "Library" section. Step 7:In the library manager window, Click on the library you just created and choose File ---> New ---> Cellview . Step 8:On the "new file" window, which popped up, enter new cell name next to the tab Cell (name it 'inverter' this time) . Make sure that the library name should be same as what you gave , view name should say "schematic" and type should say "composer-schematic". If the "type" shows something else, you can click on the button and choose "schematic". Step 9:Hit 'OK" and a schematic editing window pops up showing the library name (yourUNI), cell name (inverter) and view name which is "schematic" in this case. Step 10 : Now you are ready to draw a schematic in this window which will finally look as shown in the figure below. Look around for a few seconds and make yourself comfortable with the GUI. FIG 1 Step 11: First we will place the nmos and pmos for the CMOS inverter. Choose from the top bar, Create --> Instance . Click Browse next to library name to open the Library browser - add instance window. Choose cms9flp for the "library" , pfet for the "cell" and symbol for the "view". Now you will see a new window called "add instance" with all of the details of the pmos you will be placing down soon. Notice that there are four terminals on the pmos including the bulk/base, and the length is 100nm.. This is close to the smallest possible channel length (90nm) for the IBM technology which we are using. Fill 770n in the "width single finger" and move your mouse over the schematic window. A pmos transistor symbol will follow your mouse pointer. Place the pmos device on the window and hit "Esc". Note : In cadence, whenever, you are in the middle of a command, hit "Esc" to end it. Try hitting it multiple times to make sure you are done with a command. * You can navigate the schematic with your middle mouse button. Scrolling - vertical movement Scrolling while pressing shift key - horizontal movement Scrolling while pressing ctrl key - zoom in and out Step 12 : Again choose Add --> instance (or you can press 'i') and click 'Browse'. This time find the nmos in the "cell" and 500n as the "width all fingers". Again note that there are there are four nodes in the symbol including the base. Move your mouse over the schematic window and place the nmos transistor vertically below the pmos as in FIG 1 above. * If you want to go change properties of any instance on your schematic, press the symbol and press 'q' as a shortcut. Step 13: Now we will make wiring connections. choose Create --> wire (narrow) and click on the drain of pmos. A wire segment will follow your mouse. Bring the mouse pointer over the drain of nmos and click it to complete the wire section. Hit "Esc" on your keyboard to end the command. Similarly, draw all the wires shown in blue in Fig 1. above. * The shortcut for adding wires is 'w' on your schematic screen. Step 14: Put the pins "in" and "out" by choosing Create -->pin and giving "in" and "out" for "Pin names" one by one. Make sure to choose "direction" as input for "in" and output for "out". Other options on the "add pin" form remain unchanged. Place the pins as shown in FIG 1. * Name ALL pins and nets are in lowercase letters and numbers (no special characters like # ! @ *) throughout this course! Step 15: To make this schematic a functioning inverter we need to define DC voltages at the inverter's Vdd and Ground nodes. However, as you will see in the next page, we will define them outside of this schematic to keep things simple. Instead we will replace them with additional pins named "vdd and "gnd". Follow Step 14 similarly to create these two pins, but choose "direction" as "inputOutput". This type of pin can be used both as input and output. * Again, make sure your nets are named in capital letters. Step17 :Congratulations! You have just completed your first schematic in Cadence. To check and save your design, click on the icon with a box and a check mark. You will be warned if you have any floating wires or pins. You can also perform the same function by selecting "Check and Save" from the File menu of the schematic window. Step 18: Now we will make a symbol for this schematic, just like the pmos/gnd symbols. From your Schematic Editor window, choose Create --> Cellview --> from Cellview... A new Cellview from cellview window pops up. Everything should be already set on this window by default. The library and cell names should match those of your current schematic. Make sure it looks as shown in Fig 2. Then just OK the form. Another "Symbol Generation Options " window pops up. This is where you decide where you will have your pins located on the symbol. To make it similar with our schematic, place the gnd pin at the bottom of the symbol. You can do this by erasing gnd from 'top pins' and entering gnd at 'bottom pins'. Soon after a "Symbol Editing Window" pops up with a rectangular shaped symbol of an inverter (shown in FIG 3.). This doesn't REALLY look like an inverter symbol, but it doesn't matter for simulation. If you are really keen , you can modify this symbol using the graphic tools available on this window so that it really looks like an inverter symbol but that's not mandatory. FIG 2. FIG 3. Step 19: Close both windows (schematic and symbol) and click here to move on to the simulation part . Here is a summary of some useful shortcut keys: c --- copy instance w --- draw wire m --- move instance q --- instance properties i --- add instance f --- zoom to fit (show all components in schematic) del --- remove scroll + shift --- horizontal movement scroll + ctrl --- zoom in-out right-click mouse drag --- zoom to area esc --- quit function Make sure to hit esc after each function, since some functions will continue to affect your schematic when you don't want them to. Note that you will have to select an object after you hit a function key; for example, to copy an instance, press 'c' first -> click what you want to copy -> then click again at the desired location. Spectre simulation using Cadence' Analog Design Environment Follow the Steps : 1. For every cell that needs to be tested, we will need to generate a test schematic. For an inverter, create another cell called 'inverter_test' in your current library 'yourUNI'. Create a schematic view for this cell. For your convenience, the steps are mentioned again. Click on File --> New --> CellView in the CIW window (first window that opens with the program - the window named 'virtuoso'). Then enter Library Name as yourUNI, cellname as inverter_test and View Name as Schematic. This should pop-up an empty schematic creation window. In this window, you will generate a schematic as shown below: To generate a schematic like this, you will need to go through the following steps. This assumes that you already have an inverter schematic and its symbol. 1 a. Place an instance of inverter by pressing 'i'. ( how to place an instance has already been discussed in " Cadence Schematic Editor Information" page). Make sure that you choose an inverter symbol from your library as your instance. 1 b. Place an instance for the dc voltage source. It is located in the 'Analoglib' library and under the cell name 'vdc'. Click on 'symbol' and move your cursor to the schematic to place it down, far left, as in the figure above. Press 'q', then click on the component to enter the DC voltage value. Give it a value of 1V. 1 c. Place an instance for the piece-wise linear voltage source (vpwl), which you can find in the analogLib library and cell vpwl. Enter it's properties using 'q'. The vpwl source enables you to specify voltage source as a piece-wise linear curve. Enter the voltages as discrete entries for different time instants. The number of time instants is specified by the number of pairs of points in the window below. The above entry specifies voltage source at three points with (time, voltage) values of (0,0) , (3us,0) and (3.001us,2.5) respectively. In other words we entered a voltage source with a rise transition from 0 to 1.0V at 3us, with the rise time of 0.001us. * Note that the variable box recognizes 'u' as micro, 'n' as nano, 'p' as pico, 'f' as femto, 'a' as atto. 1 d. Place an instance of a capacitor, which you can find under library AnalogLib and cell cap. A capacitor will simulate the effect of capacitive loading from the following stages. For illustration purposes, choose a value of 1pf for the capacitor. 1 e. Place the ground gnd symbol. It is under the name 'gnd' in the 'Analoglib' library. the ground symbol defines your global ground for this circuit. So we have created a test setup for the inverter, by giving it an input and having a capacitive load. Notice that by connecting a wire between 'vdc' and the VDD pin of the inverter, we have defined the top voltage value of the inverter to be 1V. 2. Now we will simulate this inverter using Spectre in the Cadence Analog Design Environment. Re-open the inverter_test schematic window if you closed it. Choose Launch --> Ade L . You will see a window as shown below. 3. 1) Choose Setup --> Simulator/Directory/Host . A Choosing Simulator/Directory/Host window pops up. Choose 'spectre' as your simulator. 2) On the same screen, we need to specify where the simulation files will be stored. Your simulation files will easily exceed several hundred Megabytes, so you don't want this in your home directory which is uploaded to the server. You can use a directory called '/space' instead, which is in the current machine you're using. Next to 'Project directory' enter ' /space/yourUNI ' . Create the directory if you have to. Click on 'Host Mode' 'local', then press OK. * Note that the /space directory is not connected to the server, so if you move to another machine you will not be able to retrieve the simulation files. If you get space limit errors while simulating, try emptying the simulation files located in your machine's /space directory. 3) Now go to Setup --> Model Libraries.... A Model library setup window pops up. Add these three lines under 'Global Model files' in the following order: /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Spectre/models/design.scs /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Spectre/models/process.scs /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Spectre/models/fixed_corner.scs 4) Go to Setup --> Temperature and check that it is set at 27 degrees Celcius. 5) Now you have set up a simulation environment. In order to reuse the current settings in further simulations, go to Session --> Save state , give it a custom name (which is names 'state1' by default), and OK the window. This state will be tied particularly to your inverter_test schematic; to load it for use with other schematics, search the directory and look for it under this schematic. 4. Choose Analyses --> choose... You can perform either dc analysis which lets you sweep a dc voltage source or you can do transient analysis by choosing tran to observe the output as a function of time. ac and noise analysis is primarily used by analog designers to measure the frequency response and the noise performance of the circuit. In this tutorial we will focus on transient analysis. So, on the Choosing analyses window, click on tran and enter the 'stop time' as 5u. Click on 'moderate' for a reasonable measurement speed. Don't forget to choose Enabled at the bottom of the screen. Before you click 'OK', go to 'Options...' and enter "0.001u" at the tab labeled 'step'. The above entries asks the circuit to perform transient simulation from 0 to 5us, with a step size of 0.001us. 5. Go to Simulation menu in the Analog Design Environment window and click on Netlist and Run. (or you can press the green play button on the toolbar at the right end) This will start simulation. ( It is important to understand what Cadence does, when you hit a Run. It first creates a raw netlist having just the top-level instances and the include files. Next it generates a final netlist by bringing in all transistor level details. And finally, it runs the Spectre simulation. You can also go through these steps manually, by first clicking on Simulation --> Netlist -->Create and then press Run. Every step will show you an intermediate netlist output for your review. If you just press Run the first and only time, it will do all of this in one step, without showing you the intermediate netlist output) . This will start the simulation process. 6. The CIW window should show " Reading Simulation Data ...... Successful", to ensure that simulation was a success. If not go to Simulation --> Output Log in your Analog Design Environment window to find out what the problem was. Your CIW and gray text windows will also contain information about warnings and errors. Now you can still continue with Cadence to view your results, which is mentioned below. 7. Go to Tools --> Calculator in the Analog Design Environment Window. A very useful tool "Calculator" will pop-up. It is a very friendly and highly resourceful graphical user interface to view simulation results. 8. On the calculator, click on vt. This means you want to select a transient voltage on your schematic. When you click vt, you will see that your schematic window comes in front and has a small message at its bottom border saying 'Select nets' for VT expression. Now you click on one of the nets in your schematic window. You will see that the screen of your calculator shows the name of the net you just selected. Like in the above figure, I have "net2" selected. Now click plot on the calculator. (It is the icon with a calculator and a blue curve.) A new Waveform window will pop up with a Voltage vs. Time plot of the net you selected. To overlap the waveform of another net onto the same plot, go back to the calculator window, click vt, select different net, then click plot. Try showing waveforms of both in and out nets on the same plot. There is another way to simply view results. Go back to the Analog Design Environment window and go to Results --> Direct Plot --> Transient Signal. The schematic will come forward and it will let you select as many nets as you want until you press 'esc' on your keyboard. Click on the two nets, in this case, the wires going into and out of the inverter symbol, then press 'esc'. Now you should see a graph of both the input and output. 9. Finally, if you plot the in and out nets of your inverter_test schematic, you will see the input and output Voltage vs. Time plots of your inverter with a load of 1pF of capacitance. Try right-clicking your mouse and dragging it to form an area which you want to zoom in. You can always go back by pressing 'f', or clicking the 'zoom to fit' button. The result is shown in the window below. The red waveform shows the input to the inverter while the blue one shows the output which as you can see is delayed due to the finite capacitive loading. Utilizing Various Tools in ADE In the example above, we plotted the delay of an inverter as a response to a nearly-step input. However, the transient analysis is only one among many powerful tools provided by ADE. In this part of the tutorial we will briefly go over a few other useful analyses tools. Fig N1 Figure N1 shows the ADE window. Notice the 1) Choose analyses button, 2) Design Variables button, and 3) Outputs section. 1. First, by clicking the 'Choose analyses' button on the bar located on the right, you can again select the desired analysis type such as transient, ac, dc, ... Fig N2 You can sweep a variable you want by either sweeping over a 'Design Variable' or a 'Component Parameter'. Let's first look at how to use the 'Component Parameter' option. For example, if you would like to make a dc voltage source sweep over a range: 1) select 'Component Parameter' as in the example 2) click on 'Select Component', and when the schematic window comes to the front, choose your voltage source 3) choose what you would like to sweep over: in this case, select 'dc'. 4) define the Sweep Range as needed, press OK. 2. Now let's find out how to define variables. Go to the schematic you are working on, and name a voltage or current source by the name you want. Below (Figure N3) is an example of naming the dc value of a voltage source 'Vds'. By typing in a non-numerical value in the instance properties window, you can define a design variable. Fig N3 Return to the ADE window, and at the 'Design Variables' area right click your mouse, then select 'Copy from Cellview'. You will see all of the variables you have defined in your schematic appear as below (Figure N4). You can sweep one of your design variables by choosing "Sweep Variable ->Design Variable" instead of "Sweep Variable -> Component Parameter" as we did previously in Figure N2. Fig N4 3. You can automate plotting selected outputs by taking advantage of the Outputs menu. Right-click the Outputs area and click Edit. Choose which variables (dc voltage, current, ...) at which nodes (nets) you would like to plot automatically after each simulation. You can even use the calculator to insert these into an output with an equation. 4. Finally, we will learn to use an extremely powerful tool called 'Parametric Analysis'. In your ADE window, go to Tools -> Parametric Analysis. A screen like below will appear: Fig N5 Double-click 'Add Variable...' and choose the design variable you want to sweep. Define your sweep parameters (type, from, to, step number, etc.) and click the green play button (Netlist and Run). This tools allows you to execute whatever analysis you have in your ADE window, but multiple times over a third variable. For instance, if you want to see how x vs. y changes over a third variable z, the Parametric Analysis will be most useful. Note that you need to automate plotting by using the 'Outputs' section before you run Parametric Analysis, in order to visualize the effect of the third variable on the recurring simulations. ecnedaC gnisu stuoyaL motsuc lluF gnitaerC rotidE tuoyaL osoutriV In this handout, we are going to learn the following : Creating Full custom Layouts using Cadence' Virtuoso Layout Editor. By now, you would have known how to enter and simulate your designs using Spectre. The next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices because it determines whether yours is a working design or a flop! There are 2 ways of doing a layout: manual and automated. Manual layout usually enables the designer to pack his devices in a smaller area compared to the automated process but it is more tedious. The automated process, on the other hand, is done using standard cells and usually takes more real estate space but it is much faster. In this tutorial, you will learn how to perform manual layouts and a simple inverter layout will be shown. Before we get into the layout, first you need to understand the design rules for layout. The design rules which we will be using is the IBM 90nm CMOS Rules. Design rules give guidelines for generating layouts. They dictate spacings between wells, sizes of contacts, minimum spacing beween a poly and a metal and many other similar rules. Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. The design rules that we will be using can be found on the VLSI lab computers at /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/doc/cms9flp.design_manual.pdf . You can read pdf's directly in the command window by typing (acroread filename.pdf). Note that the layout is very much process dependent , since every process has a certain fixed number of available masks for layout and fabrication. For the case of this tutorial, we are using a IBM 90nm CMOS process, which is an nwell process and supports one poly and more than eight metal layers. Before we proceed any further, we must specify the tech file that we will be using when running DRC and LVS checks. In your CIW window, go to IBM_PDK --> Library --> Add IBM_PDK Lib Properties. At the new window, for 'Library Name', choose 'yourUNI'. For 'Technology', choose 'cmf9flp', and for 'Number of levels of metal', choose '6_02_00_00_LB' as in the figure below. 1. Here we will create a layout for the inverter cell. In the CIW window, click on the File --> New --> CellView. Choose Library as 'yourUNI', CellName as 'inverter' and View Name as 'layout'. Make sure that type is 'layout' and Open with is 'layout XL' . Then click on the OK button. Your schematic of the inverter, an empty Layout editor window, an finally an LSW( called "Layer Selection Window") window will pop up. The LSW window will show all the layers like nwell, pwell, active etc. for the given process. An alternate way to open the layout editor window is to click on "Layout" in the View window for inverter cell in the Library manager window. Then click on File --> Open. The LSW window should look something like this: If LSW looks different, then the most probable error is that your library is not attached to the Technology Library "cms9flp". You should attach you library to this technology file as described earlier in this page. We are ready to draw objects in the layout window. Choose Connectivity --> Generate --> All from source... At the new window, you should see some tabs and some check marks. Here you can choose which objects to import from the schematic onto the layout. Go to the 'I/O Pins' tab, and under 'layer', choose 'M1 pn' in order to specify the type of metal of the pins. Be sure to click 'apply', or not the changes will not be made. Below, at 'Pin Label', check 'Create Label as: Label' and hit 'Options'. In the new Options window, enter 0.3 as height, and give 'Layer Name' as 'same as pin', and 'Layer purpose' as 'label'. Click OK twice, and blue/red boxes will appear in your layout. The four boxes in the top left corner are the pins (VDD, GND, IN, OUT). Try clicking on the red box that says 'nfet' or 'pfet'. You will see the matching components in the schematic being highlighted. Shift-f and Ctrl-f will let you display and not display the layout contents of the parametrized pmos transistor that you have just instantiated. At this stage, Your layout should look like as shown below: *don't worry, your your pins will be 'blue' unlike the above layout. A cyan box called the 'PR boundary' will also appear along with the pins and components. Click it and when it turns white meaning that it is chosen, press 'Delete'. We do not need it here. Try to move the transistors by hitting 'm' and clicking the component. You will see that the components do not move freely. Instead, they will move along certain angles and snap to the grid. Therefore, for better cursor movement, it is crucial to follow these steps: 1. Go to Options --> Display and at the box at the top right, check Grid off. Below, enter 0.01 for 'Minor Spacing' and 0.1 for 'Major Spacing'. Then insert 0.01 for both 'X snap spacing' and 'Y snap spacing'. Below that, at the box named 'Snap Modes', choose 'Create: anyAngle' and 'Edit: orthogonal'. You can save these settings by doing 'Save to' and pressing OK. 2. Go to Options --> Editor and at the top middle box, check 'none' for 'gravity'. Now move the PMOS vertically above the NMOS. When you move them, you will see a few orange lines follow. These are nets generated based on your schematic; they will help you connect the components correctly. Now that you have placed all components, you need to make connections between them to create an inverter. We also need to place substrate and n-well contacts. Before drawing any wires, you need to select the correct drawing layer from the layer selection window (LSW) . First choose "M1 drw" from LSW . Now try drawing some wires with create --> shape --> rectangle (shortcut 'r') or create --> shape --> path (shortcut 'w'). Note that drawing paths is a little tricky. You will need to practice a little bit. To end a path you have to double click with your left mouse button. Generally drawing rectangles are easier to draw and edit. If you have drawn a rectangle of any layer and need to edit its location or dimensions, press 's', then drag your cursor into a box enclosing the specific part that you want to edit. For instance, you can enclose a corner, or you can enclose an edge of the rectangle and edit accordingly. Now add in the wire connecting the drains of both nmos and pmos which will serve as the output of the inverter. Do the same for the poly connection between the gates. You can do this by choosing "pc drw" from LSW. Note that create --> shape --> path automatically chooses min. width for the path. To change this, you need to hit F3 while the command is active and an option form will appear in which you can change the width. By using 'rectangle' or 'path' , you can also make vdd and gnd buses (vdd on top of pmos and gnd on bottom of nmos) with metal layer M1. Also connect the source of pmos to this vdd bus and that of nmos to gnd bus using the 'M1 drw' layer. Note that everything is manual when drawing layouts; connecting the substrate of the pmos to Vdd should be done by hand as well. Extend the n-well of the pmos to reach into the vdd bus on the top. You can do this by using the 'NW drw' layer. One useful tool is the ruler. You can draw a ruler by hitting 'k'. With it you can align the vdd and gnd buses, and keep there sizes symmetrical. To remove all rulers on the screen, press shift + k. * If you are in the middle of any command such as 'm', 'w' or 's', hit F3 and an option form will appear specifically for that command. You can generally solve most of the problems by choosing various options from this form which can be applied to the currently active command. Then move your pins to the correct location. Have each pin in contact with an M1 layer of the same net. So your VDD pin, for instance, can be anywhere on top of your VDD bus. One important fact here is to make sure that the label moves with the pin. Each label (the pin name in text) will have an 'x' mark in its center. If this 'x' mark is not on top of the same net that the pin is, you will get an error in LVS saying 'Abort on supply error'. Now we should add vias (also called contacts), which are vertical connections between two different layers. For example, an M1_M2 via would enable conduction between the two metal layers M1 and M2. To place the substrate and n-well vias, choose create --> via . From the tab that says 'via Definition', you can choose the via that you want to use. In our inverter layout, we will need three vias: 1) connecting the 'IN' pin made of the M1 layer with the two gates made of the PC layer 2) connecting the n-well with the VDD bus M1 layer 3) connecting the NMOS substrate with the GND bus at the bottom The three locations are shown below. To add Via 1, go to Create --> Via, and select VPC_M1. Place it touching both the PC layer (red) between the two gates AND the M1 layer (blue). As you see below, there must be some area of the pc layer of layout overlapping with the pc layer of via; similarly, there must be some area of the M1 layer of layout overlapping with the M1 layer of via. An easy way to do this is to have the PC and M1 layers overlapping in the first place, and then placing the via where they overlap. Before we draw Vias 2 and 3, there are two layers to study: The RX layer (green) and the BP layer (red slashes). The layer 'RX' is the 'active layer'. It is where the doping takes place, to form Source and Drain areas for instance. If the active layer is on top of a BP layer, it represents a p-type diffusion area; if the active layer is not on top of a BP layer, it represents an n-type diffusion area. RX + BP = p-type RX by itself = n-type (usually connected to n-well) Source: http://en.wikipedia.org/wiki/File:Cmos_impurity_profile.PNG The drawing above shows us a sideview of a Pfet and Nfet put together. For the Nfet, the substrate will be of p-type and it should be connected to GND. So we will do this with a RX + BP layer connected to the GND metal layer. (Via 3) For the Pfet, the substrate will be of n-type and it should be connected to Vdd. So we will do this solely with the RX layer. However, now this needs to connected to the n-well of the Pfet. (Via 2) Let's place Via 2 first. First draw an n-well overlapping a little with the n-well of the Pfet and covering much of the VDD bus. Use the metal layer 'nw drw'. Now add a via connecting the RX(active) layer and the M1 layer on top of the Vdd bus, where M1 and NW overlap. The Via you should look for is "VRX_M1" or "VDRX_M1". The letter 'D' simply makes a via double the size, which then reduces the resistance through the contact. As long as geometric constraints allow you to, try to use a larger via to reduce parasitic resistance. Similarly, this time we can connect the bulk of the Nfet with GND (Via 3). This time we need the bulk to be of the p-type, so we need both the active layer and the BP layer. First place a VDRX_M1 via to overlap with the GND bus. Then draw a rectangle with the BP layer enclosing the via, using the layer 'BP drw'. Note that if your via + BP rectangle is far from the Nfet, it will produce additional problems such as resistance/capacitance between bulk and source/drain. So try to locate it as close as possible in further layouts. After all this exercise, your layout should look like as below : Note that you can view only desired layers by clicking the 'NV' button in your LSW window. Select desired layers by left-clicking, and deselect unwanted layers by right-clicking your mouse. Then go back to your layout screen and repeat Ctrl + f and Shift + f. This is extremely useful when trying to figure out what a cell is composed of, and also locating faulty connections. You can go back to viewing all layers by clicking on the 'AV' button. Note also that you can add new pins by hitting hitting ctrl + p. If you have deleted a pin by mistake, or want to make new pins, press ctrl + p and define desired properties. Especially watch out for the metal layer, metal type, label size and type (If your pin is of M1 pn material, label your pins with M1 ll). Summary of shortcut keys, in addition to those mentioned in the Tutorial on Schematic Editor : r --- draw rectangle w --- draw path k --- ruler s + drag cursor onto an edge or corner --- edit edges or corners of a rectangle m --- move object shift + f / ctrl + f --- display or not display layout metal contents F3 in the middle of a function --- options to that function Mentor Calibre DRC/LVS If you haven't read the CAD tool information page, READ THAT FIRST. Mentor's Calibre tool has become the de facto industry standard for layout verification. NOTE: For Calibre DRC and LVS to properly check your layout, you must have only SHAPE (and not SYM) pins defined in your layout. These must be created using the pin (pn) metal layers, rather than the drawing (dg) layers. DRC Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules. So, DRC (design rule checking) is a step taken to alert us of any violations. This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired. To reduce the amount of clutter in your home directory, first create a directory here called "calibre_drc". This is where all the files required and produced by Calibre DRC will be stored. From the layout window, choose IBM_PDK -> Checking -> Calibre -> DRC. If you do not see the IBM_PDK option, save your layout, close the window, and load it again from Library Manager. Hit Default Runset. In the 'cms9flp Environmental Variable Setup' window, for BEOL_STACK, make sure to choose 6_02_00_00_LB. Leave everything else, and press OK. If you see a 'Load runset file' window, hit OK. You will then see a series of buttons to set up the Rules, Inputs, Outputs, and Run Control for Calibre DRC. Select the "Rules" button. If you are seeing 'Rules' in the "DRC Rules File" field, you should exit out of Calibre and try again. In the "Calibre-DRC Run Directory" field, enter the path to your "calibre_drc" directory. Note that you should not double-click the folder. When you have it selected, hit OK. Select the "Inputs" button. Make the sure the "Top Cell" field contains the name of your layout. Also ensure that the file format is GDSII and that the "Export from layout viewer" box is highlighted. The name of the stream out file will be shown in the "Files" field. You can change the name if you wish. Select the "Outputs" button. Leave everything by default. Hit "Run DRC". You can overwrite the files from previous DRC runs when prompted. While DRC is running, you will be shown the transcript file that is being produced. Once DRC has finished running, the RVE window will be displayed. Read that it displays "Topcell inverter, * results (in * of * Checks)". This tells you how many errors you received. A list of all the DRC errors in each cell of your layout will be shown here in a tree format. Click on the 'Results' title tab to bring up your errors in front of your checkmarks. You can expand the tree and view each error separately. Double-clicking on an error number will have Cadence show you the location of the error in your layout. Also, right-clicking on the error number will enable you to highlight the error directly on your layout. Correct the errors and run DRC again to re-check your layout. You should also see in your CIW window a line such as "INFO (XSTRM-234): Translation completed. '0' error(s) and '1' warning(s) found." You can ignore most warnings. Fix all errors until you reach 0 errors. When you are done, as you close the Calibre DRC window, you may want to save the runset (all your settings so far including the rules file, run directory, etc.) for future repetitions. The final DRC screen should look like this: LVS As was done for DRC, create a directory called "calibre_lvs" in your root directory. This is where all the files required and produced by Calibre LVS will be stored. From the layout window, choose IBM_PDK -> Checking -> Calibre -> LVS . Click on the button that says "Default Runset", choose 6_02_00... , and OK. You will then see a series of buttons to set up the Rules, Inputs, Outputs, and Run Control for Calibre LVS. Select the "Rules" button. In the "Calibre-LVS Run Directory" field, enter the path to your "calibre_lvs" directory. Select the "Inputs" button. Then select the "Layout" tab. Make sure the "Top Cell" field contains the name of your layout. Also ensure that the file format is GDSII and that the "Export from layout viewer" box is highlighted. The other displayed options can be set to their defaults. Select the "Netlist" tab. Ensure that the "Top Cell" field contains the name of the schematic you wish to compare. Also make sure that the file format is SPICE and that the "Export from schematic viewer" box is highlighted. The other displayed options can be set to their defaults. Select the "Outputs" button. Make sure that the "Start RVE after LVS finishes" box is highlighted. Hit "Run LVS". While LVS is running, you will be shown the transcript file that is being produced. Hit OK for the "Overwrite" windows on the way. Once LVS has finished running, the RVE window will be displayed. A list of all LVS mismatches will be shown here in a tree format. As with Calibre DRC, you can expand the tree and view each mismatch separately. Correct the mismatches and run LVS again to re-check your layout and schematic. Again, save your runset for further use. Your final LVS screen should look like this: Layout parasitic extraction using Calibre PEX If you haven't read the CAD tool information page, READ THAT FIRST. In this handout, we will learn how to extract layout with Calibre PEX and simulate (with Spectre) from the extracted layout. Now that you have completed a layout, it is time to find out how good it is. The extraction takes your layout and makes a more realistic model based on physical-structural properties. For example, it would make no difference if you had a 100n long wire or 100u long wire in your schematic, but it would certainly affect its physical properties (R, C) in your layout, and hence your calibre extraction. An extraction runs DRC and LVS again, then models the parasitic components. You can use this extracted model to simulate in Spectre and compare it with the results from your schematic. Before beginning, make sure that you have run Calibre LVS the layout and the result was "clean". First make a directory in your home directory named 'calibre_pex'. IMPORTANT: Go to Calibre -> Setup -> Calibre View and enter the following directory next to "Cellmap File". /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Calibre/xRC/cms9flp.calibre.cellmap OK the window. To run Calibre PEX, choose the menu Calibre -> Run PEX. Since this is your first time running PEX, you can hit cancel when you are asked for a 'runset file'. A runset file saves all of these settings that we are about to change. On the PEX form, go to the Rules tab, and next to PEX Rules File, click the '...' .Go to this directory: /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Calibre/xRC/ and click on the file named: cms9flp_Nominal_6_02_00_00LB_detailed.xrc.cal Choose your 'calibre_pex' directory as your PEX run directory. Go to Inputs -> Netlist and check the Export from schematic viewer bullet. In outputs, change the format from ELDO to CALIBREVIEW. Change use names from to SCHEMATIC. Set the extraction type to "R + C + CC" to extract both parasitic capacitors and resistors. * If you want to be efficient when extracting larger designs, you can use C + CC to extract only capacitors. Just don't forget that this could lead to fatal design failures in the real world. Now save the above settings by going to File -> Save Runset. Enter a name like runset1 and OK the new window, and you will be able to reuse the same settings in the future by loading this runset file. Run PEX. It will take close to a minute for a simple inverter. After running, on the "Calibre View Setup" form that pops up, o Make sure that your 'Cellmap File' points to the directory /usr/tech/cms9flp/IBM_PDK/cms9flp/relIBM/Calibre/xRC/cms9flp.calibre.cellmap o Change "Calibre View Type" to "schematic" o Change "Create terminals" to "Create all terminals" o Change "Device Placement" to "Arrayed" o Change "Open Calibre Cellview" to "read-mode". Hit OK. Warnings are fine, but if you are getting ERRORs you are in trouble. Check that the pin names and net names match with the schematic and layout. Go through the steps above from scratch to make sure you have all of them correctly; one missing step could easily result in unwanted results. If you don't have any ERRORs, you will see the following screen with a parasitic diode, lots of parasitic resistors and lots of small parasitic capacitances (to the order of attoFarads = 10^-15). By zooming into one of the capacitors, you will be able to see between which nets the capacitance is being produced. This will then create a "calibre" view in cadence that is a schematic in Virtuoso, from which you can simulate. You can locate this together with your schematic, layout, and symbol files in Library Manager. Now it's time to simulate what we extracted. Open your 'inverter_test' schematic again. Open your spectre view by doing Launch -> ADE L . If you have already forgotten about spectre simulations, refer to: On-line CISL CAD tutorial on Spectre simulation through the Analog Design Environment (ADE). Load your saved state from before which includes library data, temperature, simulation data, etc. If you have not saved your spectre environment, follow the link above to go through the settings again. After that we need only change one thing to simulate our extraction rather than our schematic. Go to Setup -> Environment and at the topmost line, enter calibre before schematic, with a space separating each word. The window should look like this: Finally, hit "Netlist and run". Display your input and output transient results, and you will see a very similar result from the schematic simulation results. It is because a simple inverter does not require complicated modeling. Try comparing the two output waveforms and delay times. Quick simulation for large designs using Ultrasim If you haven't read the CAD tool information page, READ THAT FIRST. Ultrasim is a fast event-driven circuit simulation engine. It differs from Spectre in that the circuit is partitioned into a set of stages, usually defined by transistor connected together by their sources and drains (referred to as channel-connected components, CCCs, or channel-connected regions, CCRs). Only when the inputs of the CCC change is the circuit simulation engine envoked on that CCC. In addition, Ultrasim uses simplified device models to speed analysis. So you are trading off Spectre's accuracy with Ultrasim's speed. Ultrasim work very well on digital designs. For mixed-signal designs, you must use care in how the design is partitioned and the accuracy options you use to get good results on the analog pieces. This will be true for SRAM sense amps, for example, or any PLL or DLL designs. You will use Ultrasim for functional verification; that is, to run large number of patterns through your design to make sure that your design is logically correct. You may also use Ultrasim for timing verification, although it is always a good idea, given the approximate nature of the device models, to simulate at least a few patterns in Spectre. You will find, however, that Ultrasim is dramatically faster than Spectre on large designs. First, open a test schematic where you have all of your input voltages defined (ex: not your inverter schematic, but rather your inverter_test schematic) and launch 'ADE L'. Setup -> Simulator/Directory/Host. Choose UltraSim as your Simulator. Session -> Load State. Here, load a state with your three model libraries already defined. You will get the message 'you cannot load states for a different simulator'. Ignore it. Setup -> Model Libraries. Check that you have all three model libraries defined. If you don't, copy-paste again from the Spectre tutorial page. Here's what's tricky. After you switch Simulators (Ultrasim <-> Spectre) your model libraries will be reset. So whenever you open ADE L, DEFINE YOUR SIMULATOR FIRST, then modify your remaining settings. It will not help to have all of your settings ready then switch simulators. Note that you can alternate between simulating your schematic and your extraction, just as you did with Spectre. (Adding 'calibre' before 'schematic' in Setup -> Environment) Check this before you simulate so that you are aware of what you are simulating. Now it's time to play with the various degrees of tradeoff between accuracy and speed. Go to Simulations -> Options -> Analog. 'Simulation Mode' defines the level of complexity - Digital Extended is the fastest, and Spice is the slowest but most accurate. Mixed Signal may be suitable for timing delays, for example, and Digital Fast may be suitable for figuring out the logical functionality of a huge design, but of course these terms are relative. Try running faster modes to get a sense of which one you need. You can leave 'Speed Option' and 'Analog Option' as Default. Moving onto the next tab 'Algorithm', click on DC Method. You can skip DC for very large designs. The tab 'Component' has an option called MOS Method. Again, the four options are fastest on the top of the menu and gets slower as you move down. This defines the accuracy of your MOS device model. You can leave it at Analog/MS Table. Analyses -> Choose. You will see that only transient analysis and 'envlp' are available. Choose trans and define a suitable stop time. You can automatically have your outputs plotted by doing 'Outputs -> To be plotted -> Select On Schematic'. Click as many nets as needed, then press esc. Netlist and Run. If you get an error saying 'T0, T1, ... are not defined', you will most likely find that your three model libraries were not properly added. 本文来源：https://www.wddqw.com/doc/316f59c5fbc75fbfc77da26925c52cc58bd690cf.html